PhD, Electrical Engineering
Tsinghua University
Graduated with honors; Best Student Paper Award.
Santa Clara, California
Yongmei (Jenny) Zhang
Advancing AI Hardware–Software Co-Design
Director of Engineering at Modular, a Qualcomm company
GPU/CPU architect with 15+ years of industry experience designing high-performance, power-efficient silicon — from verification methodology to GPU architecture to leading engineering teams.
About
I'm a silicon architect turned engineering leader. For over fifteen years I've worked across the stack — design verification, memory subsystems, interconnects, GPU schedulers, and datacenter-scale performance analysis — at Cadence, LG Silicon Valley Lab, Intel, and NVIDIA.
Today I lead engineering at Modular, where we're building a unified AI compute layer that lets developers write once and run anywhere — the fullest expression of the hardware–software co-design philosophy that has shaped my career.
I hold a PhD in Electrical Engineering from Tsinghua University and studied machine learning at Stanford. I write here about chip architecture, ML systems, and what it takes to build both.
Experience
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Oct 2025 — Present
Director of Engineering
Modular, a Qualcomm company
Leading engineering on the unified AI compute layer — portable, high-performance AI software across diverse hardware.
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2021 — 2025
Principal GPU Architect
NVIDIA
Architectural optimization of the GPU hardware scheduler for system efficiency and reliability; time-distribution and time-precision analysis for datacenter GPUs; performance collaboration with CUDA driver and software teams.
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2018 — 2021
Interconnect Architect for Xeon Servers & SoC Bringup Manager
Intel Corporation
Architectural optimization and performance analysis for AI and datacenter workloads; data-flow modeling across design, DV, and performance teams; directed Xeon SoC bring-up.
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2013 — 2018
Design Verification / Modeling Architect
LG Silicon Valley Lab
Led verification and built a parallel-computing functional model for an AI hardware accelerator; developed last-level cache for ARM CPU/GPU memory subsystems.
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2008 — 2013
Design & Verification Consultant
Cadence Design Systems
Led UVM adoption at Qualcomm and delivered advanced verification methodology consulting and seminars to customers worldwide.
Education & Recognition
Machine Learning
Stanford University
Graduate study in machine learning and deep learning.
Patent
US20230086723A1 · 2023
“Selection of victim entry in a data structure.”
Kaggle Silver Medal
Text Normalization Challenge · 2017
Ranked in the top 17% worldwide.