PhD, Electrical Engineering
Tsinghua University
Graduated with honors; Best Student Paper Award.
I'm an engineering leader with deep roots in hardware and software architect. For decades I've worked across hardware and software stack, spanning ASIC design, UVM and formal verification, memory subsystems, interconnects, GPU schedulers, and datacenter-scale performance analysis.
Over the past year, I've focused on building a unified AI compute layer that enables high-performance inference across diverse hardware platforms. It brings together what I’ve spent my career doing: connecting hardware architecture, software, and system performance to make AI computing faster and more efficient.
I hold a PhD in Electrical Engineering from Tsinghua University and studied machine learning at Stanford. I write here about chip architecture, ML systems, and what it takes to build both.
Oct 2025 — Present
Modular, a Qualcomm company
Leading engineering on the unified AI compute layer — portable, high-performance AI software across diverse hardware.
2021 — 2025
NVIDIA
Architectural optimization of the GPU hardware scheduler for system efficiency and reliability; time-distribution and time-precision analysis for datacenter GPUs; performance collaboration with CUDA driver and software teams.
2018 — 2021
Intel Corporation
Architectural optimization and performance analysis for AI and datacenter workloads; data-flow modeling across design, DV, and performance teams; directed Xeon SoC bring-up.
2013 — 2018
LG Silicon Valley Lab
Led verification and built a parallel-computing functional model for an AI hardware accelerator; developed last-level cache for ARM CPU/GPU memory subsystems.
2008 — 2013
Cadence Design Systems
Led UVM adoption at Qualcomm and delivered advanced verification methodology consulting and seminars to customers worldwide.
Tsinghua University
Graduated with honors; Best Student Paper Award.
Stanford University
Graduate study in machine learning and deep learning.
US20230086723A1 · 2023
“Selection of victim entry in a data structure.”
Text Normalization Challenge · 2017
Ranked in the top 17% worldwide.
Notes on AI hardware–software co-design, chip architecture, and engineering leadership.
First posts coming soon.